NANOSCALE SEQUENTIAL CIRCUITS WITH CLOCK INHERENT CAPABILITY

The current CMOS technologies have been replaced by the QCA (Quantum-Dot Cellular Automata) which is the innovative nanotechnology developing in the trending world. This technology consumes low power due to the Coulomb interaction as it doesn’t consume electric current. This model of designing the sequential circuit is a difficult strategy in the ground of Quantum Dot Cellular Automata (QCA) technology. The proposed work includes the new scheme of the pulse generator with the D-Flip Flop (FF) with the inherent characteristic in the Quantum Dot Cellular Automata (QCA) execution. This scheme includes the designing of a Novel Frequency Divider Circuit using D-Flip Flop. The implemented Novel Frequency Divider developed using an N-bit binary synchronous counter. The proposed method is implemented using the QCA Designer software which analyzes the proposed designed circuits with the simulation results. The performance analysis is mainly based on the power consumption which is verified using the QCA Designer E tool. With the investigation with the existing methods, the proposed scheme gives the minimum power and better performance factors.

CMOS technology made an innovative change in the scaling factor due to the increment in the integration density. The difficulty level increases with the decrement in the transistor size which rises increment in the power consumption and reliability factors investigated by Compano.R et al. (1999). Innovative nanotechnology design such as Quantum-Dot Cellular Automata (QCA) Technology or Carbon Nanotubes (CNTs) involves the various factors which would overcome the existing defects. By considering the Quantum-Dot Cellular Automata (QCA) technology, power consumption is low due to the elimination of electric current which tends to carry information about the logic operations. The designed Quantum-Dot Cellular Automata (QCA) Technology includes the parameters such as 2–18 nm length studied in Lent C.S et al. (1993), which is lesser than the channel length of the CMOS fabrication technique.

The range of the Quantum-Dot Cellular Automata (QCA) Technology tends to measure as THz realized in Amlaniet al. (1997). Flip Flop (FF) is the major element which is used in the sequential circuit designing. Sequential circuits with the Quantum-Dot Cellular Automata (QCA) Technology decreases the reliability difficulties in terms of designing circuits and synchronous factors. In the designing field, various research works were carried out in the Flip Flop (FF) design. Flip Flop designing mainly depends upon the area and the latency factors which implies a decrease in power consumption. No regular or symmetric designing structure is considered for the designing of Flip Flop (FF) in the Quantum-Dot Cellular Automata (QCA) Technology. The inconsistency in the various design of Flip Flop (FF) arise the technical problems such as the same circuit having a different Flip Flop (FF). By the Inter-connection of various Flip Flops types (FF) is the major complexity that arises the larger area consumption and the latency problems.

Various surveys have been undergone based on the information and the computational analysis of the system which is named as the memory-in-motion described in Amlani et al (1999) and processing-by- wire by Toth et al. (1999). The observation is carried out that the ultrahigh-density factor can increase the performance of the devices which tends to be faster and increase more speed of the devices with the lesser input power. Combinational circuits are designed based on the Quantum-Dot Cellular Automata (QCA) Technology implies the proper arrangement of cell in a series manner. The existing methodologies explain the variety of implementations of Quantum-Dot Cellular Automata (QCA) Technology designs studied in Wang et al. (2003) with some of the disadvantages. In the other phase, by considering the conventional sequential design, Flip Flops (FF) plays a major role in the designing structure.

The sequential circuits majorly comprise registers and counters which is used widely in the designing field. The characteristic of counters within the system involves the two factors namely dividing frequency and counting pulse. Although various surveys have been undergone the analysis of conventional designs used within the digital system by Yang et al(2010). The proposed paper implies the novel vigorous Quantum-Dot Cellular Automata (QCA) design with the usage of D-Flip Flop (D-FF) with a pulse generator circuit and in conclusion designed counters based on frequency divider with the single-layer method.

This paper discusses the following section which would clearly explain the designing of the Quantum-Dot Cellular Automata (QCA) design with the usage of D-Flip Flop (D-FF) with a pulse generator circuit. Section II includes the overall analysis of Quantum-Dot Cellular Automata (QCA) technology for designing circuits. Section III and IV include the State-of-Art for Quantum-Dot Cellular Automata (QCA) with D type Flip Flop and counter designing. The Designed structure is analyzed using the QCA software tool which is discussed in Section V. Conclusion and discussions were carried out in Section VI with the possible future implementation methods.

Quantum-Dot Cellular Automata

The Quantum-Dot Cellular Automata (QCA) technology is the emerging nanotechnology that includes the basic concepts that the electron pair decides the logic states without the inclusion of voltage levels. The following section discusses the basic analysis of logic states by the electron pair within the designing structure.

2.1. Quantum-Dot Cellular Automata (QCA) Architecture
The basic study of the Quantum-Dot Cellular Automata (QCA) technology depends upon the cell structure and the inclusions within the cell structure. The QCA cell comprises four quantum dots which are in the form of a square arrangement. The QCA cell is categorized into two types based on the angle of the electron placed within the cell. The Fig 1(a) and Fig 1(b)represent the various types of QCA cell which are positioned at the square-shaped with the electrons at the corner. Each QCA cell is provided with the extra movable electrons which tunnel together with the dots represented within the QCA cell. As the power consumption is reduced due to the columbic repulsion between the two electrons which makes the device a bi-state manner. Bi-state is represented as the -1 (binary logic 0) and +1 (binary logic 1) which is represented in Fig 2.

Quantum-Dot Cellular Automata (QCA) technology consists of basic wiring structure which connects the two QCA cell. With the connection of two QCA cell, there is an intermediate force developed within the cell which is named as a columbic interactions which convert binary wave towards output form. As Fig 2.2 shows, the wire can interconnect the two QCA cells with the QCA wire which is positioned within the nearby places. If the neighborhood cell tends to be represented as one in the binary input then the output of the QCA cell will be one and if it is represented as zero, then the output will be zero. The representation of the QCA cell is shown in Fig 3. The columbic repulsion between the electrons which is placed within the QCA cell has the same polarization of opposite polarization. The represented Fig 3(a) and Fig 3(b) show two types of QCA technology which differ in the arrangement of electrons within the cell structure.

Design of Inverter and majority gate with the QCA technology

The basic functional unit of QCA technology mainly consists of three parts namely Majority Gate (MG), Inverter, and the n-bit synchronous counter. Most of the nanotechnology consists of the QCA unit which mainly comprises Majority Gate (MG), Inverter circuit. The Majority Gate (MG) includes the n number of Quantum-Dot Cellular Automata (QCA) cells which are represented in Fig 2.3 (a) and Fig 2.3 (b). For the three-input majority gate(MG), the output can be expressed in terms of the majority of inputs. It is represented as Maj(A, B, C) = AB + BC + AC.The majority gate can be implemented using five QCA cells. For this structure, any one of the inputs set as zero(with the polarization value as -1), the majority gate performs as AND gate. Similarly, if any one of the inputs set as 1(with the polarization value as +1), the majority gate performs as an OR gate. Based on that structure both AND gate and OR gate can be performed with the same number of QCA cells as the majority gate. Based on the number of transistors used in the MOSFET technology, inputs within the Majority Gate (MG) can be allotted. In the MOSFET technology, more Majority Gate (MG) is considered with the various input parameters from other gates. By the usage of various Boolean gates such as NAND or NOR within the Majority Gate (MG) in terms of inverter circuit. The complexity level of the QCA design is less as compared with the other nanotechnology unit which innovates the new arithmetic functional unit. Fig 4 represents the inverter gate and the Majority Gate (MG) with the placement electrons in a squared manner.

Clocking and Crossover QCA technologies

QCA clock is mainly used to synchronize the QCA circuits and to control information flow between the cells. Clocking is also delivered the power to outing the circuit. The QCA clocking can be talented by directing the potential barriers between neighboring cells. QCA clocking is done with four phases: hold, release, relax and switch. In the switch phase, QCA cells begin gradually polarized with low potential barriers but the barriers are raised during this stage. In the hold phase, the barriers are held high while in the release stage, the barriers are lowered. In the past stage, namely relax, the barriers stay sunk and keep the cells in an unpolarized state. The four-phase clocking scheme is represented in Fig 5.

The QCA crossover structure has high compassion for to design of circuits and needs a high accuracy for the QCA cell assignment. QCA crossover techniques are categorized into two namely coplanar crossovers and multilayer crossover. The coplanar crossover uses two cell types (regular and rotated with 45 degrees) with only one layer. In this crossover the two QCA wires do not relate, meaning that the information along one QCA wire (regular cells) will not act together with another crossed QCA wire (rotated cells). But in multilayer crossover uses more than one layer (Fully regular type cells). In this type, the cells arranged one on the peak like a ladder, and then the information can be communicated from lower layer cells to upper layer cells without defecting the signals.

QCA Technology with various types of Flip-Flop

The execution of sequential circuits in QCA technology is based on the various parameters such as high-speed, low-power consumption, and consistency studied in Sheikhfaalet al. (2015). QCA technology has various existing application based on their architectural complexity and synchronous mechanism with a sequential technology. Due to the increase in the significance of sequential circuits, the power consumption will be low. In this sequential circuit, Flip-Flop plays a major role in the significance of the system. Due to the changes in the inherent capabilities, QCA planning in Flip-Flop (FF) is subdivided into line-based and loop-based structural design. As the complexity wants to be lower, the design should come under the category of loop-based or line-based design.

Previous QCA D-type flip-flops

QCA technology has built with D-flip flop consist of wire with delay. However, it’s not efficient to construct a sequential circuit. Because of timing and synchronization constraints in implementing sequential circuits. To change the cause’s clock is attached with external input to QCA flip flops. Based on that constraint D flip flop is combined with QCA technology. The implementation of the concept is shown below.

In Vettethet al. (2003) D-FF level-triggered implementation of QCA is a loop oriented structure and output resembles to clock input and The optimization of QCA D-FF technology has coplanar wire crossing scheme is used. Pictorial representation of the QCA layout is shown in Fig. 7. Meantime loop-oriented D-FF implemented with 90° QCA cells has no crossover wires shown in Figs. 8 and 9 respectively. The output has sensitive for the input clock signal is positive. QCA multiplexer uses a loop-oriented design. The implementation for majority gate based design D-FF presented inRezaeiet al. (2010) and Abutaleb (2017) and represented in Fig. 11 and 12. It has a low cell count compared to line-based design of flip flop.

Proposed QCA D-type flip-flop

Pulse generator with D-FF is introduced in QCA implementation. The countermeasures
depend on frequency divider with clock input. D and CLK were the inputs with memory elements and output of (Q) shown with a graphic symbol, gate-based structure in Fig.13 (a), 13(b) and 13(c). It has various workings whereas input D into Q and keeps the same Q. In Eq. (2) Logical functions pulse generation in D-FF is expressed. Because of major components of QCA Circuits and design equation is formulation depends on majority voter gates as shown in Eq.(3).

Q = CLK. D+CLK. Qtt-1 (2)
Q = Maj(Maj (CLK ,D,0) Maj (CLK ,Qtt-1,0), ‘1’) (3)

The implementation of D-FF is shown in Table 1. Based on the table, CLK (clock) is stimulated by 1 with input D stores in output Q. And CLK is reversed by 0 output remains the same.

Planned QCA Counter

Divide-by-2 Counters
It has the ability to Dtype logic flip flop meanwhile logical and digital circuit gives a method of cut down of incoming pulse train by two factors. These results in two and one from logic D type element and formally inserting pulse to grow up in clock circuit and coupling Qbar output to the D input, and output from the Q coupling to D type. Its simple way to train pulse from incoming side works as a clock for device and data for D input and clocked for output. To watch out the scenario the waveforms are shown below and in the case, if Q output level 1 it represents Qbar output to 0. And the Data is clock from side to side yield Q on the subsequently optimistic edge on training pulse from the input clock meantime output changes to 0. Again repeats the Qbar output is clocked again. And it is 1 opposite of Q output similarly the states changes repeatedly with changes in Output. It tends to be seen that the yield of the path just changes state on the positive-going edges of the approachheartbeat clock flow. Every positive border happens just the once each cycle, except as the yield of the D type requires two change to finish a series; it implies that the yield from the D-type circuit changes at a large portion of the pace of the approaching heartbeat pulse train. Inside additional terminology, it has be separated hooked on two. The QCA base separate by 2 contradict diagram and QCA plan is illustrated in Fig. 15(a) and 15(b).

Proposed QCA based on n-bit asynchronous counter

The proposed technique mainly includes the n-bit synchronous counter which is used to design the sequential circuits. As the counter consists of a bit synchronous counter which includes the clock synchronization pulses and the combinational circuits which are used to generate the 2n counter in the form of ascending order. By the level of the circuits which is represented in the form of D-FF with the reduction in noise level during the clock signal. The counter analysis is majorly depending such as high-speed, low-power consumption, and consistency upon the register or pattern generator which is characteristics of special output which is based on the various binary sequences. The binary sequence which is acts as an input signal is represented as the clock signal. This clock signal is used to transfer data from input towards the output system.

The increment in the count value as one or many gives the classification range of asynchronous n-counter and the synchronous counter. Counters are formed by connecting the n number of input signals towards the output signal which is called ad the “cascaded” or “divide by n counter” where the n within the counter represents the number of stages within the counter basis. Both the stages above represents the modulus or ‘MOD’ which counts the states of the output which return the input value itself.

The diagrammatic representation of the proposed paper consists of the following n bit asynchronous counter using frequency divider concept as shown in Fig.16.In this paper, The proposed QCA layout design for 2 bit and n bit counter in QCA technology is presented in Fig 17(a) and Fig 17(b).

RESULT AND DISCUSSION
This section explains the proposed Quantum Dot Cellular Automata with the D flip Flop (QCA D-FF) are designed and simulated using the QCA tool and their functionality is examined using the parameters such as the number of QCA cells, area, latency, and power dissipation.
5.1. Performance Analysis of Proposed QCA D-FF Structures

The performance analysis of the proposed QCA with D-FF is shown in Fig.14 which is represented in the form of a waveform. The output waveform is explained as the clock sequences. This clock sequence is represented as every clock cycle with the gain as a zero bit. Input waveform with the various binary bit values is represented as variable D. The logic starts with the initialization of clock (CLK) as a bit value ‘1’ that is transmitted towards the output waveform which is represented as variable Q. The output remains unchanged as there is a change in the waveform. The simulated waveform for pulse generator and the simulation waveform of D flip-flops are represented in Fig.18 and Fig.19. The simulation results are carried out with different CLK levels.

Table 1 explains the theoretical analysis and the accuracy of the results are carried out from the analysis of that tabulation. The polarization value tends to be ±9.87e-001 at the output level. The waveform of the proposed divide by 2-counter is represented in Fig 20 with the input and the output bits. The polarization rate of the 2 bit counter approximately ranges from ±9.94e-001 at the output waveform is represented in Fig 21. It is examined that the proposed QCA D-FF has a higher polarization rate and the accuracy level increases. The rectangular box within the system represents the states such as 0(00) to 4(11). This simulation result shows the efficiency of the proposed QCA implementation. The simulation study differentiates the complexity of the QCA structures from the existing designs.

From the above simulation results, it is carried out that the power of the proposed work decreases as compared with the existing work. This analysis was made using the QCA Designer and QCA Designer-E tool which is explained in Table 2 and Table 3. According to the observation with the various simulation results, the proposed design has a lesser complexity with the lesser power dissipation. The proposed QCA D-FFcan be used with the advancement in the digital system due to the lower dissipation of power and the latency.

CONCLUSION

The proposed work attempts for the first time in designing the novel vigorous Quantum-Dot Cellular Automata (QCA) design with the usage of D-Flip Flop (D-FF) and the n-bit asynchronous counter. The efficiency of the designing factor depends upon the power and the implementation complexity that can be demonstrated using the QCA Designer-E tool. The implemented technology involves the metric factor such as Quantum-Dot Cellular Automata (QCA) cell design, coverage area, latency factor of the circuit, and the power consideration. By considering Table 2 and Table 3, it can be demonstrated that Quantum-Dot Cellular Automata with D- Flip Flop (QCA D-FF) which is the proposed technique has higher efficiency as compared with the existing designing scheme. The counter is also considered as the major factor in the designing factor as they cover the wide-area within the circuit. Thus, the simulation results of the implemented work showed that it has lesser cell consumption, minimum area coverage, increment in the polarization factor with the decrement in the delay factor. The major use of the proposed method is in the construction of high-speed digital systems due to the decrement in power consumption and increment in the performance analysis.